1. Field of Invention
The present invention relates to a memory structure and a manufacturing method thereof. More particularly, the present invention relates to a mask read-only-memory (mask ROM) structure and its method of manufacture.
2. Description of Related Art
Most mask read-only-memory (mask ROM) comprises a plurality of bit lines (BL) and a plurality of word lines (WL) running across and above the bit lines. The channel region of each memory cell is located underneath the word lines and between two neighboring bit lines. For some mask ROM, programming involves planting ions into some of the memory cell channels so that a data bit xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is stored in the memory cell. The process of planting ions into specified channel regions is often called a coding implant.
In general, the coding implant for a mask ROM is carried out in a few steps. First, a photoresist layer is formed over a substrate and the photoresist layer is patterned using a photomask so that the channel regions where an ion implantation is desired are exposed. Thereafter, using the patterned photoresist layer as a mask, ions are implanted into the exposed channel regions. However, the photomask that serves as a coding mask in the code implant process for producing the mask ROM may contain both isolated pattern regions and dense pattern regions. While transferring the pattern in a photo-exposure operation, average intensity of the light falling on the photoresist in the isolated pattern regions is stronger than average intensity of light falling on the dense pattern regions. Consequently, critical dimensions of the exposed pattern may deviate from the standard values due to optical proximity effect (OPE) between the isolated pattern regions and the dense pattern regions. Thus, when ions are implanted into the designated channel regions to program the mask ROM, misalignment of the implanted ions may occur leading to possible data error in some ROM cells. As a result, operating properties of each ROM cell may vary and overall reliability of the mask ROM may drop.
To minimize the non-uniformity of critical dimensions after pattern exposure due to the presence of both dense pattern regions and isolated pattern regions in the coding mask, an optical proximity correction (OPC) method or a phase shift mask (PSM) technique is often deployed. In the optical proximity correction (OPC) method, a specially designed auxiliary pattern is introduced to eliminate critical dimension deviation caused by proximity effect. However, to implement the correction, a photomask with specially designed pattern must be produced. Since the photomask is expensive and difficult to make, overall production cost is increased. Moreover, debugging the defects in the pattern after fabrication is extremely difficult.
Furthermore, if the coding mask in the coding implant process is misaligned or if the critical dimensions have some deviation, the coding ions originally intended for the channel regions may diffuse into the buried bit lines. When this happens, ion concentration within the buried bit lines may change leading to a reduction of current flow in the buried bit lines.
Accordingly, one object of the present invention is to provide a mask read-only-memory (mask ROM) structure and its method of manufacture capable of preventing the diffusion of coding ions into buried bit lines in the mask ROM and the subsequent reduction of current flow in the buried bit lines.
A second object of this invention is to provide a mask read-only-memory structure and its method of manufacture capable of preventing critical dimension deviations in isolated pattern regions and dense pattern regions when a conventional coding implant process for programming the memory cells inside the mask ROM is deployed.
A third object of this invention is to provide a mask read-only-memory structure and its method of manufacture capable of programming the mask ROM while employing neither the optical proximity method nor the phase shifting mask technique, thereby reducing production cost.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a mask read-only-memory (mask ROM) structure. The mask ROM includes a substrate, a buried bit line, a patterned stack layer, a gate oxide layer and a word line. The buried bit line is embedded inside the substrate. The stack layer covers a portion of the upper surface of the substrate. The stack layer comprises a first dielectric layer, a stopping layer and a second dielectric layer. In this invention, the first dielectric layer and the second dielectric layer are, for example, silicon oxide layer. The stopping layer is, for example, a silicon nitride layer or a silicon oxynitride layer. The gate oxide layer covers a portion of the upper surface of the substrate. The word line runs over and across the buried bit line to form a plurality of coding memory cells. Among the coding cells, the ones having a stack layer thereon are at a logic state xe2x80x9c0xe2x80x9d while the ones having a gate oxide layer thereon are at a logic state xe2x80x9c1xe2x80x9d.
This invention also provides a method of manufacturing a mask read-only-memory (mask ROM). A first dielectric layer, a stopping layer and a second dielectric layer are sequentially formed over a substrate to form a stack layer. The first dielectric layer and the second dielectric layer are silicon oxide layers and the stopping layer is a silicon nitride or a silicon oxynitride layer, for example. Using the stack layer as an implant mask, an ion implantation is carried out to form a buried bit line in the exposed substrate. A first photoresist layer is formed over the substrate. The first photoresist layer has a first line/distance pattern thereon. In this invention, the first line/distance pattern comprises a plurality of trenches running perpendicular to the buried bit line. The second dielectric layer and the stopping layer outside the first photoresist layer are removed to expose the first dielectric layer. Thereafter, the first photoresist layer is removed and a second photoresist layer is formed over the substrate. The second photoresist layer has a second line/distance pattern. The second line/distance pattern extends in a direction different from the first line/distance pattern. In this invention, the second line/distance pattern extends in a direction perpendicular to the first line/distance pattern. The second line/distance pattern comprises a plurality of trenches parallel to the buried bit line. Using the second photoresist layer and the stopping layer as an etching mask, a portion of the second dielectric layer and the first dielectric layer are removed to expose the substrate and the stopping layer. A gate oxide layer is formed over the exposed substrate. A word line is formed over the substrate in a direction perpendicular to the buried bit line, thereby forming a plurality of coding cells. Among the coding cells, the ones having a stack layer thereon are at a logic state xe2x80x9c0xe2x80x9d while the ones having a gate oxide layer thereon are at a logic state xe2x80x9c1xe2x80x9d.
The mask ROM structure according to this invention is programmed not by a coding implant process. Hence, the problem of having coding ions diffusing into the buried bit line resulting in a reduction in the current-carrying capacity in the bit line is entirely eliminated.
In this invention, the memory cells inside the mask ROM structure are programmed through patterning the stack layer. Thus, the non-uniformity of critical dimensions in the isolated pattern regions and dense pattern regions resulting from using a conventional method to form a coding mask layer is prevented.
The mask ROM structure according to this invention is manufactured without using either the optical proximity correction method or the phase shift mask technique. Hence, cost of producing the mask ROM is lowered considerably.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.